1. Field of the Invention
The present invention relates to a semiconductor memory device including an ECC (Error Checking and Correcting) circuit.
2. Description of the Prior Art
In recent years, higher integration for implementing a SOC (System On Chip) at a low cost has been particularly required of an embedded DRAM (Dynamic Random Access Memory). Since a memory array portion occupies a majority of a memory area, the area of each memory cell has been reduced by means of a technology for miniaturizing a memory cell transistor and a memory capacitor using a high-dielectric-constant insulating film in order to implement higher integration.
When a stacked memory cell is miniaturized, the surface area of a capacitor is accordingly reduced so that a sufficient capacitance is ensured for the capacitor by introducing a novel high-dielectric-constant insulating film. However, to increase the capacitance of the capacitor, the thickness of the insulating film should be minimized, which increases a tunnel leakage current in the capacitor insulating film. In addition, because of a strong demand for logic compatibility in the miniaturization process mentioned above, a storage node has been silicidized, which increases a junction leakage in the storage node. As a result, the deterioration of the charge retention time of a cell has presented a problem. In addition, there has also been a requirement for provision against degraded reliability resulting from the reduced charge retention time of a cell, an increased cell access time, each due to post-fabrication variations with time in the characteristics of a cell capacitor and a cell transistor, or the like. It is known that, to improve the degraded reliability of a cell, a method using ECC is useful.
As an example of a known technology related to a semiconductor memory device including an ECC circuit, the specification of US Patent Application Publication No. 2006/0112321 discloses a sequence method wherein, to implement an error correcting operation with a byte write function, a word line and a sense amplifier are continuously activated in a serial sequence which performs a data read operation, and a write back operation of writing, back to a memory cell, replaced data obtained by replacing a part of error corrected data with external data as well as parity data generated from the replaced data.
In Japanese Laid-Open Patent Publication No. 2003-59290, a structure is shown which replaces m bits forming a part of n-bit error corrected read data with external input data, and performs a write back operation in order to implement an error correcting operation with a byte write function.
Further, in Japanese Laid-Open Patent Publication No. 2005-25827, a structure is shown which performs a read-modify-write operation in order to implement an ECC operation with a byte mask function in an SDRAM (Synchronous DRAM). The structure allows midway interruption of the inputting of burst data by completing syndrome generation and error correction during read latency, preparing error corrected read data during read latency, and performing parity generation and a write back operation in each burst cycle after a lapse of read latency.
In Japanese Laid-Open Patent Publication No. 2006-244632, a structure is shown which performs a pipeline read-modify-write operation in order to implement an ECC operation with a byte mask function in an SDRAM. To prevent a data collision in a bus during a read operation prior to a write operation and during a write back operation of writing back data and parity data, the structure divides DQ lines into those for a read operation and those for a write operation. Alternatively, the structure separately performs a read operation and a write operation in an even-numbered cycle and an odd-numbered cycle of a burst operation.
In the case where stored data is read in each of the semiconductor memory devices, a multiple bit signal is read first from a memory cell array in accordance with a row address, and amplified and held by a sense amplifier (RAS (Row Address Strobe) Cycle)). Thereafter, a signal composed of some of the foregoing plurality of bits selected therefrom in accordance with a column address in a column gate is inputted to an ECC circuit via a buffer, subjected to error detection and correction, and outputted as read data from the semiconductor memory device (CAS (Column Address Strobe) cycle).
However, in the case where some of a plurality of bits read from a memory cell array are selected in accordance with a column address as described above, the foregoing selection, error detection and correction, and the like are performed after the column address is determined. This leads to the problem that it is difficult to reduce CAS access time and, therefore, it is also difficult to increase the speed of a memory access.